View LIS2HH12_8830413.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. december 2015 docid025344 rev 5 1/47 LIS2HH12 mems digital output motion sensor: ultra-low-power high-performance 3-axis "pico" accelerometer datasheet - production data features ? wide supply voltage, 1.71 v to 3.6 v ? independent ios supply (1.8 v) and supply voltage compatible ? ultra-low power consumption ?? 2g/ ? 4g/ ? 8 g full-scale ? i 2 c/spi digital output interface ? 16-bit data output ? embedded temperature sensor ? embedded self-test ? embedded fifo ? 10000 g high shock survivability ? ecopack ? , rohs and ?green? compliant applications ? motion-controlled user interfaces ? gaming and virtual reality ? pedometers ? intelligent power saving for handheld devices ? display orientation ? click/double-click recognition ? impact recognition and logging ? vibration monitoring and compensation description the LIS2HH12 is an ultra-low-power high- performance three-axis linear accelerometer belonging to the ?pico? family. the LIS2HH12 has full scales of ? 2g/ ? 4g/ ? 8g and is capable of measuring accelerations with output data rates from 10 hz to 800 hz. the self-test capability allows the user to check the functioning of the sensor in the final application. the LIS2HH12 has an integrated first-in, first-out (fifo) buffer allowing the user to store data in order to limit intervention by the host processor. the LIS2HH12 is available in a small thin plastic land grid array package (lga) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c lga-12 (2.0x2.0x1.0 mm) table 1. device summary order codes temperature range [ ? c] package packaging LIS2HH12 -40 to +85 lga-12 tray LIS2HH12tr -40 to +85 lga-12 tape and reel www.st.com
contents LIS2HH12 2/47 docid025344 rev 5 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 activity/inactivity function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 data stabilization time / odr change . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.5 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid025344 rev 5 3/47 LIS2HH12 contents 47 5.3.6 bypass-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.7 retrieving data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.8 fifo multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1 temp_l (0bh), temp_h (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 act_ths (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.4 act_dur (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 ctrl1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 ctrl2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.7 ctrl3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8 ctrl4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.9 ctrl5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10 ctrl6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.11 ctrl7 (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.12 status (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.13 out_x_l (28h) - out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.14 out_y_l (2ah) - out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.15 out_z_l (2ch) - out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.16 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.17 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.18 ig_cfg1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.19 ig_src1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.20 ig_ths_x1 (32h), ig_ths_y1 (33h), ig_ths_z1 (34h) . . . . . . . . . . . . 40
contents LIS2HH12 4/47 docid025344 rev 5 8.21 ig_dur1 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.22 ig_cfg2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.23 ig_src2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.24 ig_ths2 (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.25 ig_dur2 (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.26 xl_reference (3ah), xh_reference (3bh) . . . . . . . . . . . . . . . . . 42 8.27 yl_reference (3ch), yh_reference (3dh) . . . . . . . . . . . . . . . . . 42 8.28 zl_reference (3eh), zh_reference (3fh) . . . . . . . . . . . . . . . . . . 42 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 lga-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 lga-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
docid025344 rev 5 5/47 LIS2HH12 list of tables 47 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted . . . . . . . . . 10 table 4. electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted . . . . . . . . . . . 11 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. activity/inactivity function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. number of samples to be discarded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 13. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25 table 17. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25 table 18. register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. who_am_i register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 20. act_ths register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. act_dur register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 23. control register 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24. odr register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25. low-pass cutoff frequency in high resolution mode (hr = 1) . . . . . . . . . . . . . . . . . . . . . . . 32 table 26. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 27. control register 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 28. control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. control register 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30. control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 31. control register 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 32. control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 33. control register 5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 34. self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 35. control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 36. control register 6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 37. control register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 38. control register 7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 39. status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 40. status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 41. fifo control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 42. fifo control register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 43. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 44. fifo status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 45. fifo status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 46. ig_cfg1 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 47. ig_cfg1 configuration register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 48. ig1_src1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables LIS2HH12 6/47 docid025344 rev 5 table 49. ig1_src1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 50. ig1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 51. ig1_ths description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 52. ig_dur1 duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 53. ig_dur1 duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 54. ig_cfg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 55. ig_cfg2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 56. ig_src2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 57. ig_src2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 58. ig_ths2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 59. ig_ths2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 60. ig_dur2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 61. ig_dur2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 62. lga-12 2x2x1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 63. reel dimensions for carrier tape of lga-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 64. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
docid025344 rev 5 7/47 LIS2HH12 list of figures 47 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. i 2 c slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. LIS2HH12 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 6. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. fifo multiple reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. lga-12 2x2x1 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 15. carrier tape information for lga-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. lga-12 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17. reel information for carrier tape of lga-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
block diagram and pin description LIS2HH12 8/47 docid025344 rev 5 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connections charge amplifier y+ z+ y- z- a x+ x- i2c spi cs scl/spc sda/sdi/sdo sdo/sa0 int1 clock trimming circuits reference self test a/d converter1 int2 mux control logic temp. sensor fifo a/d converter2 (top view) direction of the detectable accelerations x 1 y z vdd_io sc l/spc sda/sdi/sdo cs sdo/sa0 res gnd int1 int2 res vdd res (bottom view) pin 1 indicator 4 1 5 7 11 8 res res 12 14 gnd sc l/spc sda/sdi/sdo cs sdo/sa0 gnd res int 1 vdd_io (bottom view) 4 1 5 6 gnd 11 int 2 7 10 vdd 12
docid025344 rev 5 9/47 LIS2HH12 block diagram and pin description 47 table 2. pin description pin# name function 1 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 2cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 3 sdo sa0 spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) 4 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 5 res connect to gnd 6 gnd 0 v supply 7 gnd 0 v supply 8 gnd 0 v supply 9 vdd power supply 10 vdd_io power supply for i/o pins 11 int2 interrupt pin 2 12 int1 interrupt pin 1
mechanical and electrical specifications LIS2HH12 10/47 docid025344 rev 5 2 mechanical and electrical specifications 2.1 mechanical characteristics table 3. mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit fs measurement range (3) 2.0 g 4.0 g 8.0 g so sensitivity @ fs 2.0 g 0.061 m g /digit @ fs 4.0 g 0.122 m g /digit @ fs 8.0 g 0.244 m g /digit tcso sensitivity change vs. temperature 0.01 %/c tyoff typical zero- g level offset accuracy (4) 30 m g tcoff zero- g level change vs. temperature (4) delta from 25 c 0.25 m g /c ton turn-on time number of samples to be discarded from power-down to active mode ctrl4 (23h) (bw_scale_odr) = 0 1 # of samples st self-test positive difference (5) 70 1500 m g to p operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.71 v to 3.6 v. 2. typical specifications are not guaranteed. 3. verified by wafer level test and measurement of initial offset and sensitivity. 4. offset can be eliminated by enabling the built-in high-pass filter. 5. ?self-test positive difference? is defined as: output[m g ] (ctrl5 st2, st1 bits=01) - output[m g ] ( ctrl5 st2, st1 bits=00 ) .
docid025344 rev 5 11/47 LIS2HH12 mechanical and electrical specifications 47 2.2 electrical characteristics 2.3 temperature sensor characteristics @ vdd =2.5 v, t=25 c unless otherwise noted table 4. electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 1.71 2.5 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idda current consumption in active mode odr 100-800 hz 180 a odr 50 hz 110 a odr 10 hz 50 a iddpdn current consumption in power-down mode 5 a vih digital high-level input voltage 0.8*vdd_io v vil digital low-level input voltage 0.2*vdd_io v tboot boot time (4) 20 ms top operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.71 v to 3.6 v. 2. typical specifications are not guaranteed. 3. it is possible to remove vdd maintaining vdd_io without blocking the communication busses, in this condition the measurement chain is powered off. 4. time to complete the entire boot sequence: from vdd on until all configuration and calibration parameters are correctly loaded into device registers. table 5. temperature sensor characteristics symbol parameter min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature 8 digit/c (2) todr temperature refresh rate 10 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. 11-bit resolution.
mechanical and electrical specifications LIS2HH12 12/47 docid025344 rev 5 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. table 6. spi slave timing values symbol parameter value (1) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 6 ns t h(cs) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 9 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. spc cs sd i sd o t su ( cs) t v( so ) t h( so ) t h( si ) t su ( si ) t h( cs) t di s( so ) t c( spc) msb i n msb out lsb out lsb i n
docid025344 rev 5 13/47 LIS2HH12 mechanical and electrical specifications 47 2.4.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production sd a scl t su(sp) t w(scll) t su(sda) t su(sr) t h(st) t w(sclh) t h(sda) t w(sp:sr) start repea ted sta rt stop sta rt
mechanical and electrical specifications LIS2HH12 14/47 docid025344 rev 5 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3000 for 0.5 ms g 10000 for 0.2 ms g a unp acceleration (any axis, unpowered) 3000 for 0.5 ms g 10000 for 0.2 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
docid025344 rev 5 15/47 LIS2HH12 mechanical and electrical specifications 47 2.6 terminology and functionality terminology 2.6.1 sensitivity sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. as the sensor can measure dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.6.2 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on the x-axis and 0 g on the y-axis whereas the z-axis will measure 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement number). a deviation from ideal value in this case is called zero- g offset. offset is to some extent a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. functionality 2.6.3 self-test the self-test allows checking the sensor functionality without moving it. the self-test function is off when the self-test bits (st) are programmed to ?00?. when the self-test bits are changed, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2.7 sensing element a proprietary process is used to create a surface micromachined accelerometer. the technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. in order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation.
factory calibration LIS2HH12 16/47 docid025344 rev 5 when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady-state the nominal value of the capacitors are a few pf and when an acceleration is applied, the maximum variation of the capacitive load is in the ff range. 2.8 ic interface the complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage using an analog-to-digital converter. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS2HH12 features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. 3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (tyoff). the trim values are stored inside the device in nonvolatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. this allows using the device without further calibration.
docid025344 rev 5 17/47 LIS2HH12 application hints 47 4 application hints figure 5. LIS2HH12 electrical connections the device core is supplied through the vdd line while the i/o pads are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to pin 9 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to remove vdd while maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data are selectable and accessible through the i 2 c or spi interfaces. when using the i 2 c, cs must be tied high (i.e. connected to vdd_io). the functions, the threshold and the timing of the two interrupt pins (int1 and int2) can be completely programmed by the user through the i 2 c/spi interface. 4.1 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com . digital signal from/to signal controller.signal levels are defined by proper selection of vdd_io vdd_io 10f vdd 100nf gnd res sc l/spc sda/sdi/sdo cs sdo/sa0 gnd gnd int 1 vdd_io 4 1 6 5 gnd 11 int 2 7 10 vdd 100nf 12
digital main blocks LIS2HH12 18/47 docid025344 rev 5 5 digital main blocks 5.1 activity/inactivity function the activity/inactivity recognition function allows reducing the power consumption of the system in order to develop new smart applications. when the activity/inactivity recognition function is activated, the LIS2HH12 is able to automatically go to 10hz sampling rate and to wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility. the activity/inactivity recognition function is activated by writing the desired threshold in the act_ths (1eh) register. the high-pass filter is automatically enabled. when the acceleration falls below the threshold for a duration of at least (8 act_dur +1)/odr, the ctrl1 (20h) (odr [2:0]) bits of ctrl1 are bypassed (inactivity) and internally set to 10hz (odr [2:0] = 001), but the content of the ctrl1 (20h) (odr [2:0]) bits are left untouched. when the acceleration exceeds the threshold ( act_ths (1eh) ), the odr setting in ctrl1 (20h) is restored immediately (activity). once the activity/inactivity detection function is enabled, the status can be brought out on int1 by setting the ctrl3 (22h) (int1_inact) bit to 1. to disable the activity/inactivity detection function, set the content of the act_ths (1eh) register to 00h. table 9. activity/inactivity function control registers register lsb value act_ths full scale / 128 [m g ] act_dur 8/odr [s]
docid025344 rev 5 19/47 LIS2HH12 digital main blocks 47 5.2 data stabilization time / odr change the data stabilization time required when an odr change is applied in order to have valid usable data depends on the bw and odr selected. the table below provides the number of samples to be discarded in order to obtain valid usable data. 5.3 fifo the LIS2HH12 embeds an acceleration data fifo for each of the three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work according to the following different modes: bypass mode, fifo-mode, stream mode, stream-to-fifo mode, bypass-to-stream, bypass-to-fifo. each mode is selected by the fifo_mode bits in the fifo_ctrl (2eh) register. programmable fifo threshold level, fifo empty or fifo overrun events are available in the fifo_ctrl (2eh) register and can be set to generate dedicated interrupts on the int1 or int2 pin. fifo_src (2fh) (empty) is equal to '1' when no samples are available. fifo_src (2fh) (fth) goes to '1' if new data arrives and fifo_src (2fh) (fss [4:0]) is greater than or equal to fifo_ctrl (2eh) (fth [4:0]). fifo_src (2fh) (fth) goes to '0' if reading x, y, z data slot from fifo and fifo_src (2fh) (fss [4:0]) is less than or equal to fifo_ctrl (2eh) (fth [4:0]). fifo_src (2fh) (ovr) is equal to '1' if a fifo slot is overwritten. the fifo feature is enabled by writing the ctrl3 (22h) (fifo_en) bit to '1' in control register 3. in order to guarantee the correct acquisition of data during the switching into and out of fifo mode, the first sample acquired must be discarded. 5.3.1 bypass mode in bypass mode ( fifo_ctrl (2eh) (fmode [2:0])= 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode. table 10. number of samples to be discarded odr [hz] bw = 400 hz bw = 200 hz bw = 100 hz bw = 50 hz 101--- 501--- 1001111 2001114 4001147 80014714
digital main blocks LIS2HH12 20/47 docid025344 rev 5 5.3.2 fifo mode in fifo mode ( fifo_ctrl (2eh) (fmode [2:0])= 001) data from the x, y and z channels are stored in the fifo until it is full. an overrun interrupt can be enabled, ctrl3 (22h) (int1_ovr)= '1', in order to be raised when the fifo stops collecting data. when the overrun interrupt occurs, the first set of data has been overwritten and the fifo stops collecting data from the input channels. to reset the fifo content, bypass mode should be written in the fifo_ctrl (2eh) register, setting the fmode [2:0] bits to '000'. after this reset command, it is possible to restart fifo mode, writing the value '001' in fifo_ctrl (2eh) (fmode [2:0]). the fifo buffer can memorize 32 slots of x, y and z data, but the depth of the fifo can be reduced using the ctrl3 (22h) (stop_ fth) bit. setting the stop_fth bit to '1', fifo depth is limited to fifo_ctrl (2eh) (fth [4:0]) - 1. 5.3.3 stream mode stream mode ( fifo_ctrl (2eh) (fmode [2:0]) = 010) provides a continuous fifo update: as new data arrives, the older data is discarded. an overrun interrupt can be enabled, ctrl3 (22h) (int1_ovr) = '1', in order to read the entire content of the fifo at once. if in the application no data can be lost and it is not possible to read at least one sample for each axis within one odr period, a watermark interrupt can be enabled in order to read partially the fifo and leave free memory slots for incoming data. setting the fifo_ctrl (2eh) (fth [4:0]) to value n, the number of x, y and z data samples that should be read at the rise of the watermark interrupt is up to (n+1). in the latter case, reading all fifo content before an overrun interrupt has occurred, the first data read is equal to the last data already read in previous burst, so the number of new data available in the fifo depends on the previous reading (see fifo_src (2fh) behavior depicted in the following figures). figure 6. stream mode
docid025344 rev 5 21/47 LIS2HH12 digital main blocks 47 a watermark interrupt ctrl3 (22h) (int1_fth), ctrl6 (25h) (int2_fth) can be enabled in order to read data from the fifo and leave free memory slots for incoming data. setting the fifo_ctrl (2eh) (fth [4:0]) to value n, the number of x, y and z data samples that should be read at the rise of the watermark interrupt, in order to read the entire fifo content, is n + 1. 5.3.4 stream-to-fifo mode in stream-to-fifo mode ( fifo_ctrl (2eh) (fmode2:0) = 011), fifo behavior changes according to the ig_src1 (31h) (ia) bit. when the ig_src1 (31h) (ia) bit is equal to '1' fifo operates in fifo mode, when the ig_src1 (31h) (ia) bit is equal to '0', fifo operates in stream mode. interrupt generator 1 should be set to the desired configuration using ig_cfg1 (30h) , ig_ths_x1 (32h), ig_ths_y1 (33h), ig_ths_z1 (34h) . the ctrl7 (26h) (lir1) bit should be set to '1' in order to have latched interrupt. 5.3.5 bypass-to-stream mode in bypass-to-stream mode ( fifo_ctrl (2eh) (fmode [2:0]) = '100'), x, y and z measurement storage inside fifo operates in stream mode when ig_src1 (31h) (ia) is equal to '1', otherwise fifo content is reset (bypass mode). interrupt generator 1 should be set to the desired configuration using ig_cfg1 (30h) , ig_ths_x1 (32h), ig_ths_y1 (33h), ig_ths_z1 (34h) . the ctrl7 (26h) (lir1) bit should be set to '1' in order to have latched interrupt. 5.3.6 bypass-to-fifo mode in bypass-to-fifo mode ( fifo_ctrl (2eh) (fmode [2:0]) = '111', fifo behavior changes according to the ig_src1 (31h) (ia) bit. when the ig_src1 (31h) (ia) bit is equal to '1', fifo operates in fifo mode, when the ig_src1 (31h) (ia) bit is equal to '0', fifo operates in bypass mode (fifo content reset). if a latched interrupt is generated, fifo starts collecting data until the first data in the fifo buffer is overwritten. interrupt generator 1 should be set to the desired configuration using ig_cfg1 (30h) , ig_ths_x1 (32h), ig_ths_y1 (33h), ig_ths_z1 (34h) . the ctrl7 (26h) (lir1) bit should be set to '1' in order to have latched interrupt. 5.3.7 retrieving data from fifo fifo data is read through the out_x_l (28h) - out_x_h (29h) , out_y_l (2ah) - out_y_h (2bh) , out_z_l (2ch) - out_z_h (2dh) registers. a read operation by means of serial interface of out_x, out_y or out_z output registers provides the data stored into the fifo. each time data is read from the fifo, the oldest x, y and z data are placed into the out_x, out_y and out_z registers and both single read and read_burst operations can be used.
digital main blocks LIS2HH12 22/47 docid025344 rev 5 5.3.8 fifo multiple reads (burst) starting from addr 28h multiple reads can be performed. once the read reaches addr 2dh the system automatically restarts from addr 28h. figure 7. fifo multiple reads x,y,z out_z read #1 (2c-2d) (2a-2b) out_y (28-29) out_x x,y,z read #n out_z (2c-2d) (2a-2b) out_y (28-29) out_x
docid025344 rev 5 23/47 LIS2HH12 digital interfaces 47 6 digital interfaces the registers embedded inside the LIS2HH12 may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped to the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the LIS2HH12 i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through an external pull- up resistor. when the bus is free, both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. in order to disable the i 2 c block, ctrl4 (23h) (i2c_disable) = 1 must be set. table 11. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0 sdo i 2 c address selection (sa0) spi serial data output (sdo) table 12. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces LIS2HH12 24/47 docid025344 rev 5 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS2HH12 is 00111xxb where the xx bits are modified by the sa0/sdo pin in order to modify the device address. if the sa0/sdo pin is connected to the supply voltage, the address is 0011101b, otherwise if the sa0/sdo pin is connected to ground, the address is 0011110b. this solution permits to connect and address two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LIS2HH12 behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted: the 7 lsb represents the actual register address while the ctrl4 (23h) (if_add_inc) bit defines the address increment. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes. if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 13 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 13. sad+read/write patterns command sad[6:2] sad[1] = sa0 sad[0] = sa0 r/w sad+r/w read 00111 1 0 1 00111 101 write 00111 1 0 0 00111 100 read 00111 0 1 1 00111 011 write 00111 0 1 0 00111 010 table 14. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
docid025344 rev 5 25/47 LIS2HH12 digital interfaces 47 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the LIS2HH12 spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 8. read and write protocol table 15. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 16. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 17. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 ad6
digital interfaces LIS2HH12 26/47 docid025344 rev 5 cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands additional blocks of 8 clock periods will be added. when the ctrl4 (23h) (if_add_inc) bit is ?0?, the address used to read/write data remains the same for every block. when the ctrl4 (23h) (if_add_inc) bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 6.2.1 spi read figure 9. spi read protocol the spi read command is performed with 16 clock pulses. a multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). additional data in multiple byte reads. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
docid025344 rev 5 27/47 LIS2HH12 digital interfaces 47 figure 10. multiple byte spi read protocol (2-byte example) 6.2.2 spi write figure 11. spi write protocol the spi write command is performed with 16 clock pulses. a multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). additional data in multiple byte writes. figure 12. multiple byte spi write protocol (2-byte example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15do14do13do12do11do10do9 do8 ad6 cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ad6 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ad6
digital interfaces LIS2HH12 28/47 docid025344 rev 5 6.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the ctrl4 (23h) (sim) bit equal to ?1? (spi serial interface mode selection). figure 13. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
docid025344 rev 5 29/47 LIS2HH12 register mapping 47 7 register mapping the table given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses. table 18. register map name type register address default comment hex binary reserved r 00-0a - reserved temp_l r 0b 00001011 output temp_h r 0c 00001100 output reserved r 0e - reserved who_am_i r 0f 00001111 01000001 who i am id act_ths r/w 1e 00011110 00000000 act_dur r/w 1f 0001 1111 00000000 ctrl1 r/w 20 00100000 00000111 control registers ctrl2 r/w 21 00100001 00000000 ctrl3 r/w 22 00100010 00000000 ctrl4 r/w 23 00100011 00000100 ctrl5 r/w 24 00100100 00000000 ctrl6 r/w 25 00100101 00000000 ctrl7 r/w 26 00100110 00000000 status r 27 00100111 output status data register out_x_l r 28 00101000 output output registers out_x_h r 29 00101001 out_y_l r 2a 00101010 out_y_h r 2b 00101011 out_z_l r 2c 00101100 out_z_h r 2d 00101101 fifo_ctrl r/w 2e 00101110 00000000 fifo registers fifo_src r 2f 00101111 output ig_cfg1 r/w 30 00110000 00000000 interrupt generator 1 configuration ig_src1 r 31 00110001 output interrupt generator 1 status register ig_ths_x1 r/w 32 00110010 00000000 interrupt generator 1 threshold x
register mapping LIS2HH12 30/47 docid025344 rev 5 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ig_ths_y1 r/w 33 00110011 00000000 interrupt generator 1 threshold y ig_ths_z1 r/w 34 00110100 00000000 interrupt generator 1 threshold z ig_dur1 r/w 35 00110101 00000000 interrupt generator 1 duration ig_cfg2 r/w 36 00110110 00000000 interrupt generator 2 configuration ig_src2 r 37 00110111 output interrupt generator 2 status register ig_ths2 r/w 38 00111000 00000000 interrupt generator 2 threshold ig_dur2 r/w 39 00111001 00000000 interrupt generator 2 duration xl_ reference r/w 3a 00111010 00000000 reference x low xh_ reference r/w 3b 00111011 00000000 reference x high yl_ reference r/w 3c 00111100 00000000 reference y low yh_ reference r/w 3d 00111101 00000000 reference y high zl_ reference r/w 3e 00111110 00000000 reference z low zh_ reference r/w 3f 00111111 00000000 reference z high table 18. register map (continued) name type register address default comment hex binary
docid025344 rev 5 31/47 LIS2HH12 register description 47 8 register description 8.1 temp_l (0bh), temp_h (0ch) temperature output register (r). the value is expressed in two?s complement. 8.2 who_am_i (0fh) who_am_i register (r). this register is a read-only register. its value is fixed at 41h. 8.3 act_ths (1eh) activity threshold register (r/w). its value is fixed at 0x00. inactivity threshold. 8.4 act_dur (1fh) activity duration register (r/w). its value is fixed at 0x00. activity duration. 8.5 ctrl1 (20h) control register 1(r/w) table 22. control register 1 table 23. control register 1 description table 19. who_am_i register default values 01000001 table 20. act_ths register default values 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 21. act_dur register default values dur7 dur6 dur5 dur4 dur3 dur2 dur1 dur0 hr odr2 odr1 odr0 bdu zen yen xen hr high resolution bit. default value: 0 0: normal mode, 1: high resolution (see table ) odr [2:0] output data rate & power mode selection . default value: 000 (see table ) bdu block data update. default value: 0 0: continuous update; 1:output registers not updated until msb and lsb read) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) yen y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled)
register description LIS2HH12 32/47 docid025344 rev 5 odr [2:0] is used to set the power mode and odr selection. the following table lists the bit settings for power-down mode and each available frequency. the bdu bit is used to inhibit the update of the output registers until both upper and lower register parts are read. in default mode (bdu = ?0?) the output register values are updated continuously. when the bdu is activated (bdu = ?1?), the content of the output registers is not updated until both msb and lsb are read which avoids reading values related to different sample times. table 24. odr register setting odr2 odr1 odr0 power-down and odr selection 0 0 0 power-down 0 0 1 10 hz 0 1 0 50 hz 0 1 1 100 hz 1 0 0 200 hz 1 0 1 400 hz 1 1 0 800 hz 1 1 1 n.a. table 25. low-pass cutoff frequency in high resolution mode (hr = 1) hr ctrl2 (dfc [1:0]) lp cutoff freq. [hz] 1 00 odr/50 1 01 odr/100 1 10 odr/9 1 11 odr/400
docid025344 rev 5 33/47 LIS2HH12 register description 47 8.6 ctrl2 (21h) control register 2 (r/w) table 26. control register 2 table 27. control register 2 description 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. dfc1 dfc0 hpm1 hpm0 fds hpis1 hpis2 dfc1 [1:0] high-pass filter cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected odr and on the settings of the dfc [1:0] bits hpm [1:0] high-pass filter mode selection. default value: 00 ?00? or ?10? = normal mode; ?01? = reference signal for filtering; ?11? = not available fds high-pass filter data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpis1 high-pass filter enabled for interrupt generator function on interrupt 1. default value: 0 (0: filter bypassed; 1: filter enabled) hpis2 high-pass filter enabled for interrupt generator function on interrupt 2. default value: 0 (0: filter bypassed; 1: filter enabled)
register description LIS2HH12 34/47 docid025344 rev 5 8.7 ctrl3 (22h) control register 3 (r/w). int1 control register. table 28. control register 3 table 29. control register 3 description 8.8 ctrl4 (23h) control register 4 (r/w) table 30. control register 4 fifo_en stop_fth int1 _inact int1 _ig2 int1 _ig1 int1 _ovr int1 _fth int1 _drdy fifo_en fifo enable. default value 0. (0: disable; 1: enable) stop_fth enable fifo threshold level use. default value 0. (0: disable; 1: enable) int1_inact inactivity interrupt on int1. default value 0. (0: disable; 1: enable) int1_ig2 interrupt generator 2 on int1. default value 0. (0: disable; 1: enable) int1_ig1 interrupt generator 1 on int1. default value 0. (0: disable; 1: enable) int1_ovr fifo overrun signal on int1. int1_fth fifo threshold signal on int1. int1_drdy data ready signal on int1. bw2 bw1 fs1 fs0 bw_scale_odr if_add_inc i2c_disable sim table 31. control register 4 description bw [2:1] anti-aliasing filter bandwidth. default value: 00 (00: 400 hz; 01: 200 hz; 10: 100 hz; 11: 50 hz) fs [1:0] full-scale selection. default value: 00 (00: 2 g ; 01: not available; 10: 4 g ; 11: 8 g ) bw_scale_odr if '0', bandwidth is automatically selected as follows: bw = 400 hz when odr = 800 hz, 50 hz, 10 hz; bw = 200 hz when odr = 400 hz; bw = 100 hz when odr = 200 hz; bw = 50 hz when odr = 100 hz; if '1', bandwidth is selected according to bw [2:1] excluding odr = 50 hz, 10 hz, bw = 400 hz if_add_inc register address automatically incremented during multiple byte access with a serial interface (i 2 c or spi). (0: disabled; 1: enabled) i2c_disable disable i 2 c interface. default value: 0 (0: i 2 c enabled; 1: i 2 c disabled) sim spi serial interface mode selection. default value: 0 0: 4-wire interface; 1: 3-wire interface
docid025344 rev 5 35/47 LIS2HH12 register description 47 8.9 ctrl5 (24h) control register 5 (r/w) table 32. control register 5 debug soft_reset dec1 dec0 st2 st1 h_lactive pp_od table 33. control register 5 description debug debug stepping action selected. default value: 0 (0: disabled; 1: enabled) soft_reset soft reset, it acts as por when 1, then goes to 0 dec [1:0] decimation of acceleration data on out reg and fifo 00 -> no decimation 01 -> update every 2 samples 10 -> update every 4 samples 11 -> update every 8 samples st [2:1] self-test enable. default value: 00 (00: self-test disabled; other: see table below) h_lactive interrupt active high, low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open-drain selection on interrupt pad. default value: 0 (0: push-pull; 1: open-drain) table 34. self-test mode selection st2 st1 self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 negative sign self-test 1 1 not allowed
register description LIS2HH12 36/47 docid025344 rev 5 8.10 ctrl6 (25h) control register 6 (r/w) table 35. control register 6 8.11 ctrl7 (26h) control register 7 (r/w) table 37. control register 7 boot 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. int2 _boot int2 _ig2 int2 _ig1 int2 _empty int2 _fth int2 _drdy table 36. control register 6 description boot force reboot, cleared as soon as the reboot is finished. active high. default value 0. int2_boot boot interrupt on int2. default value: 0 (0: disable; 1: enable) int2_ig2 interrupt generator 2 on int2. default value: 0 (0: disable; 1: enable) int2_ig1 interrupt generator 1 on int2. default value: 0 (0: disable; 1: enable) int2_empty fifo empty flag on int2. default value: 0 int2_fth fifo threshold signal on int2. default value: 0 int2_drdy data ready signal on int2. default value: 0 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) dcrm2 dcrm1 lir2 lir1 4d_ig2 4d_ig1 table 38. control register 7 description dcrm [2:1] dcrm is used to select the reset mode of the duration counter. default value: 0 if dcrm = ?0?, the counter is reset when the interrupt is no longer active, else if dcrm = ?1? the duration counter is decremented. 1lsb lir [2:1] latched interrupt [2:1] default value: 00 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading the ig_src1 (31h) and ig_src2 (37h) registers. 4d_ig [2:1] interrupt [2:1] 4d option enabled. default value: 00 when set, ig_cfg1 (30h) and ig_cfg2 (36h) use 4d for position recognition.
docid025344 rev 5 37/47 LIS2HH12 register description 47 8.12 status (27h) status register (r/w) table 39. status register 8.13 out_x_l (28h) - out_x_h (29h) x-axis output register (r) 8.14 out_y_l (2ah) - out_y_h (2bh) y-axis output register (r) 8.15 out_z_l (2ch) - out_z_h (2dh) z-axis output register (r) zyxor zor yor xor zyxda zda yda xda table 40. status register description zyxor x-, y- and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set) zor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x-, y- and z-axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x-axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available)
register description LIS2HH12 38/47 docid025344 rev 5 8.16 fifo_ctrl (2eh) fifo control register (r/w) table 41. fifo control register the fifo trigger is the ig_src1 (31h) event. (refer to ig_src1 (31h) ). 8.17 fifo_src (2fh) fifo status control register (r) table 44. fifo status register table 45. fifo status register description fmode2 fmode1 fmode0 fth4 fth3 fth2 fth1 fth0 table 42. fifo control register description fmode [2:0] fifo mode selection bits. default: 000. for further details refer to table below fth [4:0] fifo threshold. default: 00000. it is the fifo depth if the stop_fth bit in the ctrl3 (22h) register is set to ?1?. table 43. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stops collecting data when fifo is full. 0 1 0 stream mode. if the fifo is full, the new sample overwrites the older one 0 1 1 stream mode until trigger is deasserted, then fifo mode 1 0 0 bypass mode until trigger is deasserted, then stream mode 1 0 1 not used 1 1 0 not used 1 1 1 bypass mode until trigger is deasserted, then fifo mode fth ovr empty fss4 fss3 fss2 fss1 fss0 fth fifo threshold status. 0: fifo filling is lower than fth level; 1: fifo filling is equal to or higher than threshold level ovr overrun bit status. 0: fifo is not completely filled; 1: fifo is completely filled empty fifo empty bit. 0: fifo not empty; 1: fifo empty) fss [4:0] fifo stored data level
docid025344 rev 5 39/47 LIS2HH12 register description 47 8.18 ig_cfg1 (30h) interrupt generator 1 configuration register (r/w) table 46. ig_cfg1 configuration register table 47. ig_cfg1 configuration register description 8.19 ig_src1 (31h) interrupt generator 1 status register (r) table 48. ig1_src1 register table 49. ig1_src1 register description aoi 6d zhie zlie yhie ylie xhie xlie aoi and/or combination of interrupt events. default value: 0 6d 6-direction detection function enabled. default value: 0 zhie enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) ylie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xhie enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xlie enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) - ia zhzlyhylxhxl ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) zh z high. default value: 0 (0: no interrupt; 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred)
register description LIS2HH12 40/47 docid025344 rev 5 8.20 ig_ths_x1 (32h), ig_ths_y1 (33h), ig_ths_z1 (34h) interrupt generator 1 threshold registers (r/w) table 50. ig1_ths register table 51. ig1_ths description 8.21 ig_dur1 (35h) interrupt generator 1 duration register (r/w) table 52. ig_dur1 duration table 53. ig_dur1 duration description 8.22 ig_cfg2 (36h) interrupt generator 2 configuration register (r/w) table 54. ig_cfg2 register table 55. ig_cfg2 register description ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths [7:0] interrupt 1 thresholds. default: 00000000 wait1 dur1_6 dur1_5 dur1_4 dur1_3 dur1_2 dur1_1 dur1_0 wait1 wait function enable on duration counter. default value: 0 (0: wait function off; 1: wait function on) dur1_[6:0] duration value default: 0000000 aoi 6d zhie zlie yhie ylie xhie xlie aoi and/or combination of interrupt events. default value: 0 6d 6-direction detection function enabled. default value: 0 zhie enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) ylie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xhie enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xlie enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request)
docid025344 rev 5 41/47 LIS2HH12 register description 47 8.23 ig_src2 (37h) interrupt generator 2 status register (r) table 56. ig_src2 register table 57. ig_src2 register description 8.24 ig_ths2 (38h) interrupt generator 2 threshold register (r/w) table 58. ig_ths2 register table 59. ig_ths2 register description 8.25 ig_dur2 (39h) interrupt generator 2 duration register (r/w) table 60. ig_dur2 register table 61. ig_dur2 register description - ia zhzlyhylxhxl ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events has been generated) zh z high. default value: 0 (0: no interrupt; 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred) ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths [7:0] interrupt generator 2 thresholds. default 00000000 wait2 dur2_6 dur2_5 dur2_4 dur2_3 dur2_2 dur2_1 dur2_0 wait2 wait function enable on duration counter. default value: 0 (0: wait function off; 1: wait function on) dur2_[6:0] duration value. default: 0000000
register description LIS2HH12 42/47 docid025344 rev 5 8.26 xl_reference (3ah), xh_reference (3bh) in normal mode (hpm [1:0] = ?00? or ?10?) when one of these registers (xl_reference or xh_reference) is read, the x output of the hp filter is set to ?0?. in reference mode (hpm [1:0] =?01?) the reference value is subtracted from the x output of the hp filter. 8.27 yl_reference (3ch), yh_reference (3dh) see previous section concerning the x reference (r/w) registers. 8.28 zl_reference (3eh), zh_reference (3fh) see previous section concerning the x reference (r/w) registers.
docid025344 rev 5 43/47 LIS2HH12 package information 47 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 lga-12 package information figure 14. lga-12 2x2x1 package outline table 62. lga-12 2x2x1 package mechanical data ref. min. typ. max. a1 1 a2 0.785 a3 0.200 d1 1.850 2.000 2.150 e1 1.850 2.000 2.150 l1 1.500 n1 0.500 t1 0.275 t2 0.250 p2 0.075 r 45 m 0.100 k 0.050 8365767_a
package information LIS2HH12 44/47 docid025344 rev 5 9.2 lga-12 packing information figure 15. carrier tape information for lga-12 package figure 16. lga-12 package orientation in carrier tape
docid025344 rev 5 45/47 LIS2HH12 package information 47 figure 17. reel information for carrier tape of lga-12 package table 63. reel dimensions for carrier tape of lga-12 package reel dimensions (mm) a (max) 330 b (min) 1.5 c 13 0.25 d (min) 20.2 n (min) 60 g 12.4 +2/-0 t (max) 18.4 $ ' % )x o o u dg l x v 7dshvorw lqfruhiru wdshvwduw ppplqzlgwk *phdvxuhgdwkxe & 1 ppplq $ffhvvkrohdw vorworfdwlrq 7
revision history LIS2HH12 46/47 docid025344 rev 5 10 revision history table 64. document revision history date revision changes 26-nov-2013 1 initial release 27-nov-2013 2 general document review 24-sep-2014 3 document status promoted from preliminary to production data updated figure 2: pin connections and figure 5: LIS2HH12 electrical connections added table 9: activity/inactivity function control registers 09-nov-2015 4 added section 9.2: lga-12 packing information 14-dec-2015 5 updated hpis1 and hpis2 bits in ctrl2 (21h) updated table 8: absolute maximum ratings updated figure 17: reel information for carrier tape of lga-12 package
docid025344 rev 5 47/47 LIS2HH12 47 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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